Abstract:
The wireless communication medium requires employing forward error correction methods on the data transferred, where Reed-Solomon & Viterbi coding techniques are generally utilized, because of performance and security reason. In this paper we present a modular design of phase encoding these codes for concatenation using System Generator of Xilinx and oriented to implementation with field programmable gate arrays (FPGA). The work begins with a review of code concept and the definition of the components and the model and the description of the behavioral. Later, the architecture is made based in model based design. The scheme of FEC will be done according to the specifications of the DVB standard for the digital Digital television.
